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A single-transistor silicon synapse

Diorio, Chris and Hasler, Paul and Minch, Bradley A. and Mead, Carver A. (1996) A single-transistor silicon synapse. IEEE Transactions on Electron Devices, 43 (11). pp. 1972-1980. ISSN 0018-9383. doi:10.1109/16.543035.

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We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory-update rule from the physics of the tunneling and injection processes, and have investigated synapse learning in a prototype array. Unlike conventional EEPROM devices, the synapse allows simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. The synapse is small, and typically is operated at subthreshold current levels; it will permit the development of dense, low-power silicon learning systems.

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Additional Information:© 1996 IEEE. Manuscript received December 5, 1995; revised April 1, 1996. The review of this paper was arranged by Editor C.-Y. Lu. This work was supported by the Office of Naval Research, by the Advanced Research Projects Agency, by the Beckman Hearing Institute, by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program, and by the California Trade and Commerce Agency, Office of Strategic Technology.
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Office of Naval Research (ONR)UNSPECIFIED
Advanced Research Projects Agency (ARPA)UNSPECIFIED
Beckman Hearing InstituteUNSPECIFIED
Center for Neuromorphic Systems EngineeringUNSPECIFIED
California Trade and Commerce Agency, Office of Strategic TechnologyUNSPECIFIED
Issue or Number:11
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ID Code:53656
Deposited On:14 Jan 2015 07:05
Last Modified:10 Nov 2021 20:05

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