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A floating-gate MOS learning array with locally computed weight updates

Diorio, Chris and Hasler, Paul and Minch, Bradley A. and Mead, Carver A. (1997) A floating-gate MOS learning array with locally computed weight updates. IEEE Transactions on Electron Devices, 44 (12). pp. 2281-2289. ISSN 0018-9383. doi:10.1109/16.644652.

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We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 μs, whereas the weight normalization takes minutes to hours.

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Additional Information:© 1997 IEEE. Manuscript received February 21, 1997; revised June 19, 1997. The review of this paper was arranged by Editor C.-Y. Lu. This work was supported by the Office of Naval Research, the Advanced Research Projects Agency, the Beckman Hearing Institute, the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program, and the California Trade and Commerce Agency, Office of Strategic Technology.
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Office of Naval Research (ONR)UNSPECIFIED
Advanced Research Projects Agency (ARPA)UNSPECIFIED
Beckman Hearing InstituteUNSPECIFIED
Center for Neuromorphic Systems EngineeringUNSPECIFIED
California Trade and Commerce Agency, Office of Strategic TechnologyUNSPECIFIED
Issue or Number:12
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Deposited On:14 Jan 2015 06:51
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