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128-bit multicomparator

Mead, Carver A. and Pashley, Richard D. and Britton, Lee D. and Daimon, Yoshiaki T. and Sando, Stewart F., Jr. (1976) 128-bit multicomparator. IEEE Journal of Solid-State Circuits, 11 (5). pp. 692-695. ISSN 0018-9200. https://resolver.caltech.edu/CaltechAUTHORS:20150114-095719979

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Abstract

A 128-bit multicomparator was designed to perform the search-sort function on arbitrary length data strings. Devices can be cascaded for longer block lengths or paralleled for bit-parallel, word-serial applications. The circuit utilizes a 3-phase static-dynamic shift register cell for data handling and a unique gated EXCLUSIVE-NOR circuit to accomplish the compare function. The compare operation is performed bit parallel between a `data' register and a `key' register with a third `mask' register containing DON'T CARE bits that disable the comparator. The multicomparator was fabricated using p-channel silicon-gate metal-oxide-semiconductor (MOS) technology on a 107/spl times/150 mil chip containing 3350 devices. With transistor-transistor logic (TTL) input, data rates in excess of 2 MHz have been attained. The average power dissipation was 250 mW in the dynamic mode and 300 mW in the static mode.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.1976.1050799DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1050799PublisherArticle
Additional Information:© 1976 IEEE. Manuscript received March 15, 1976; revised JulY 18, 1976. The authors are pleased to acknowledge Intel Corporation for wafer fabrication.
Issue or Number:5
Record Number:CaltechAUTHORS:20150114-095719979
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150114-095719979
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53685
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:14 Jan 2015 20:56
Last Modified:03 Oct 2019 07:51

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