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Cost and performance of VLSI computing structures

Mead, Carver A. and Rem, Martin (1979) Cost and performance of VLSI computing structures. IEEE Journal of Solid-State Circuits, 14 (2). pp. 455-462. ISSN 0018-9200. http://resolver.caltech.edu/CaltechAUTHORS:20150114-100150657

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Abstract

Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time product as a cost function.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.1979.1051197DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1051197PublisherArticle
Additional Information:© 1979 IEEE. Manuscript received September 18, 1978; revised January 10, 1979. This work was supported in part by BMD under Contract DASG60-77-C-0097, and the Office of Naval Research under Contract N00014-16-C-0367. (California Institute of Technology, Computer Science Department Contribution 1584.)
Funders:
Funding AgencyGrant Number
BMDDASG60-77-C-0097
Office of Naval Research (ONR)N00014-16-C-0367
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Caltech Computer Science Department1584
Record Number:CaltechAUTHORS:20150114-100150657
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20150114-100150657
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53687
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:14 Jan 2015 20:51
Last Modified:14 Jan 2015 20:51

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