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Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems

Mohsen, Amr M. and Mead, Carver A. (1979) Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems. IEEE Journal of Solid-State Circuits, 14 (2). pp. 462-470. ISSN 0018-9200. https://resolver.caltech.edu/CaltechAUTHORS:20150114-102206258

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Abstract

Minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.1979.1051198DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1051198PublisherArticle
Additional Information:© 1979 IEEE.
Issue or Number:2
Record Number:CaltechAUTHORS:20150114-102206258
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150114-102206258
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53693
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:14 Jan 2015 20:45
Last Modified:03 Oct 2019 07:51

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