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A two's complement pipeline multiplier

Cheng, Edmund K. and Mead, Carver A. (1976) A two's complement pipeline multiplier. In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '76. Vol.1. IEEE , Piscataway, NJ, pp. 647-650.

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A serial-data pipeline multiplier was designed and implemented in p-channel silicon-gate MOS. It uses a radix-4 Booth algorithm for two's complement compatibility. The circuit is modular, and is configured to multiply one data word by two coefficient words simultaneously.

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Additional Information:© 1976 IEEE. The authors wish to thank R. F. Jurgens, R. T. Maaumoto, and G. A. Morris for their assistance; Intel Corp. for fabrication of the circuits; and in particular R. F. Lyon for his invaluable contributions during the butial phase of this work.
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Intel CorporationUNSPECIFIED
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ID Code:53905
Deposited On:21 Jan 2015 05:42
Last Modified:10 Nov 2021 20:08

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