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A two's complement pipeline multiplier

Cheng, Edmund K. and Mead, Carver A. (1976) A two's complement pipeline multiplier. In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '76. Vol.1. IEEE , Piscataway, NJ, pp. 647-650. https://resolver.caltech.edu/CaltechAUTHORS:20150120-163927542

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Abstract

A serial-data pipeline multiplier was designed and implemented in p-channel silicon-gate MOS. It uses a radix-4 Booth algorithm for two's complement compatibility. The circuit is modular, and is configured to multiply one data word by two coefficient words simultaneously.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/ICASSP.1976.1169990DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1169990PublisherArticle
Additional Information:© 1976 IEEE. The authors wish to thank R. F. Jurgens, R. T. Maaumoto, and G. A. Morris for their assistance; Intel Corp. for fabrication of the circuits; and in particular R. F. Lyon for his invaluable contributions during the butial phase of this work.
Funders:
Funding AgencyGrant Number
Intel CorporationUNSPECIFIED
Record Number:CaltechAUTHORS:20150120-163927542
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150120-163927542
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53905
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:21 Jan 2015 05:42
Last Modified:03 Oct 2019 07:53

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