Lin, Tzu-Mu and Mead, Carver A. (1984) Signal Delay in General RC Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 3 (4). pp. 331-349. ISSN 0278-0070. http://resolver.caltech.edu/CaltechAUTHORS:20150120-165111914
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Abstract
Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charge are properly taken into consideration. A technique called tree decomposition and load redistribution is introduced that is capable of dealing with general RC networks without sacrificing a number of desirable properties of tree networks. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time.
| Item Type: | Article | |||||||||
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| Additional Information: | © 1984 IEEE. Manuscript received May 18, 1984; revised December 5, 1983. This work was supported by the System Development Foundation. | |||||||||
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| Record Number: | CaltechAUTHORS:20150120-165111914 | |||||||||
| Persistent URL: | http://resolver.caltech.edu/CaltechAUTHORS:20150120-165111914 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 53907 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | Kristin Buxton | |||||||||
| Deposited On: | 23 Jan 2015 23:41 | |||||||||
| Last Modified: | 23 Jan 2015 23:41 |
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