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GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction

Gojman, Benjamin and Nalmela, Sirisha and Mehta, Nikil and Howarth, Nicholas and DeHon, André (2014) GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction. ACM Transactions on Reconfigurable Technology Systems, 7 (4). Art. No. 32. ISSN 1936-7406. doi:10.1145/2597889.

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Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near-individual LUT SRAM cell granularity, characterizing components with delays on the order of tens to a few hundred picoseconds with a resolution of ±3.2ps, matching the expected error bounds. This information reveals that the 65nm process used has, on average, random variation of σ μ =4.0% with components having an average maximum spread of 83ps. Timing Extraction also shows that as V_(DD) decreases from 1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths slow down, and variation increases from σ μ =4.3% to σ μ =5.8%, a clear indication that lowering V_(DD) magnifies the impact of random variation.

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Additional Information:© 2014 Copyright is held by the owner/author(s). Publication rights licensed to ACM. Received May 2013; revised October 2013; accepted January 2014. This researchwas funded in part by National Science Foundation grant CCF-0904577. Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. The authors gratefully acknowledge donations of software and hardware from Altera Corporation that facilitated this work, as well as valuable guidance from Mike Hutton and useful pointers from Justin Wong and Joshua Levine.
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Subject Keywords:Component-specific mapping, variation measurment, variation characterization, in-system measurement
Issue or Number:4
Record Number:CaltechAUTHORS:20150121-071331821
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53908
Deposited By: Ruth Sustaita
Deposited On:21 Jan 2015 23:34
Last Modified:10 Nov 2021 20:08

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