Mead, Carver A. (1996) Scaling of MOS technology. IEEE Micro, 16 (6). p. 48. ISSN 0272-1732. doi:10.1109/40.546564. https://resolver.caltech.edu/CaltechAUTHORS:20150127-164258678
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Abstract
The MOS transistor is the workhorse of modern microelectronics. Reducing the feature size of CMOS fabrication processes has been the primary method by which ever-increasing computation could proceed at ever-decreasing cost and power consumption. How does this scaling affect device performance? Are there fundamental physical limits to how small die MOS device, as we know it today, can be scaled?
| Item Type: | Article | |||||||||
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| Additional Information: | © 1996 IEEE. | |||||||||
| Issue or Number: | 6 | |||||||||
| DOI: | 10.1109/40.546564 | |||||||||
| Record Number: | CaltechAUTHORS:20150127-164258678 | |||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20150127-164258678 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 54157 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | INVALID USER | |||||||||
| Deposited On: | 28 Jan 2015 00:46 | |||||||||
| Last Modified: | 10 Nov 2021 20:29 |
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