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A Complementary Pair of Four-Terminal Silicon Synapses

Diorio, Chris and Hasler, Paul and Minch, Bradley A. and Mead, Carver (1997) A Complementary Pair of Four-Terminal Silicon Synapses. Analog Integrated Circuits and Signal Processing, 13 (1-2). pp. 153-166. ISSN 0925-1030. https://resolver.caltech.edu/CaltechAUTHORS:20150127-165006071

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Abstract

We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We have derived a memory-update rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write and erase isolation between array synapses is better than 0.01%. The synapses are small, and typically are operated at subthreshold current levels; they will permit the development of dense, low-power silicon learning systems.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1023/A:1008244314595DOIArticle
http://link.springer.com/article/10.1023/A%3A1008244314595PublisherArticle
Additional Information:© 1997 Kluwer Academic Publishers. Received April 9, 1996; Accepted June 28, 1996. This work was supported by the Office of Naval Research, by the Advanced Research Projects Agency, by the Beckman Hearing Institute, by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program, and by the California Trade and Commerce Agency, Office of Strategic Technology.
Funders:
Funding AgencyGrant Number
Office of Naval Research (ONR)UNSPECIFIED
Advanced Research Projects Agency (ARPA)UNSPECIFIED
Beckman Hearing InstituteUNSPECIFIED
Center for Neuromorphic Systems EngineeringUNSPECIFIED
NSFUNSPECIFIED
California Trade and Commerce Agency, Office of Strategic TechnologyUNSPECIFIED
Subject Keywords:synapse transistor, silicon learning, floating-gate MOSFET
Issue or Number:1-2
Record Number:CaltechAUTHORS:20150127-165006071
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150127-165006071
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:54159
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:28 Jan 2015 06:38
Last Modified:03 Oct 2019 07:55

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