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A Charge-Based CMOS Parallel Analog Vector Quantizer

Cauwenberghs, Gert and Pedroni, Volnei (1995) A Charge-Based CMOS Parallel Analog Vector Quantizer. In: Advances in Neural Information Processing Systems 7. The MIT Press , Cambridge, MA, pp. 779-786. ISBN 0-262-20104-6.

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We present an analog VLSI chip for parallel analog vector quantization. The MOSIS 2.0 μm double-poly CMOS Tiny chip contains an array of 16 x 16 charge-based distance estimation cells, implementing a mean absolute difference (MAD) metric operating on a 16-input analog vector field and 16 analog template vectors. The distance cell including dynamic template storage measures 60 x 78 μm^2. Additionally, the chip features a winner-take-all (WTA) output circuit of linear complexity, with global positive feedback for fast and decisive settling of a single winner output. Experimental results on the complete 16 x 16 VQ system demonstrate correct operation with 34 dB analog input dynamic range and 3 μsec cycle time at 0.7 mW power dissipation.

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Additional Information:© 1995 Massachusetts Institute of Technology. Fabrication of the CMOS chip was provided through the DARPA INSF MOSIS service. The authors thank Amnon Yariv for stimulating discussions and encouragement.
Record Number:CaltechAUTHORS:20150305-152558615
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:55559
Deposited On:06 Mar 2015 05:32
Last Modified:03 Oct 2019 08:06

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