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Single Transistor Learning Synapses

Hasler, Paul and Diorio, Chris and Minch, Bradley A. and Mead, Carver (1995) Single Transistor Learning Synapses. In: Advances in Neural Information Processing Systems 7. The MIT Press , Cambridge, MA, pp. 817-824. ISBN 0-262-20104-6.

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We describe single-transistor silicon synapses that compute, learn, and provide non-volatile memory retention. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and the weight value, and update the weight value according to a Hebbian or a backpropagation learning rule. Memory is accomplished via charge storage on polysilicon floating gates, providing long-term retention without refresh. The synapses efficiently use the physics of silicon to perform weight updates; the weight value is increased using tunneling and the weight value decreases using hot electron injection. The small size and low power operation of single transistor synapses allows the development of dense synaptic arrays. We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. The synaptic array was fabricated in the standard 2μm double - poly, analog process available from MOSIS.

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Additional Information:© 1995 Massachusetts Institute of Technology. The work was supported by the office of Naval Research, the Advanced Research Projects Agency, and the Beckman Foundation.
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Office of Naval Research (ONR)UNSPECIFIED
Advanced Research Projects Agency (ARPA)UNSPECIFIED
Arnold and Mabel Beckman FoundationUNSPECIFIED
Record Number:CaltechAUTHORS:20150305-153222850
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:55561
Deposited On:06 Mar 2015 05:30
Last Modified:03 Oct 2019 08:06

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