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An 8GHz First-order Frequency Synthesizer based on Phase Interpolation and Quadrature Frequency Detection in 65nm CMOS

Saeedi, Saman and Emami, Azita (2014) An 8GHz First-order Frequency Synthesizer based on Phase Interpolation and Quadrature Frequency Detection in 65nm CMOS. In: 2014 IEEE Proceedings of the Custom Integrated Circuits Conference (CICC),. IEEE Custom Integrated Circuits Conference . IEEE , Piscataway, NJ, pp. 1-4. ISBN 978-1-4799-3286-3. https://resolver.caltech.edu/CaltechAUTHORS:20150310-075028459

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Abstract

A low-power high-speed frequency synthesizer in 65nm CMOS is presented. The design features a novel architecture combining an LC quadrature VCO, two sample-and-holds, a phase interpolator, digital coarse-tuning and a novel quadrature frequency detection technique for fine-tuning. The system works based on injecting the rising edges of reference clock. The architecture has first-order dynamics, eliminating jitter accumulation. Functionality of the frequency synthesizer was validated between 8-9.5GHz, LC VCO's range of operation. The output clock at 8GHz has an integrated rms jitter of 0.5ps and peak-to-peak periodic jitter of 2.9ps. The reference spurs are -64.3dB below the carrier frequency. The system consumes 2.49mW from a 1V supply at 8GHz.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/CICC.2014.6946021DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6946021PublisherArticle
ORCID:
AuthorORCID
Emami, Azita0000-0003-2608-9691
Additional Information:© 2014 IEEE. The authors would like to thank STMicroelectronics for chip fabrication.
Subject Keywords:Analog-digital integrated circuit; hybrid integrated circuits; interpolation; phase-locked loops
Series Name:IEEE Custom Integrated Circuits Conference
Record Number:CaltechAUTHORS:20150310-075028459
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150310-075028459
Official Citation:Saeedi, S.; Emami, A., "An 8GHz first-order frequency synthesizer based on phase interpolation and quadrature frequency detection in 65nm CMOS," Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the , vol., no., pp.1,4, 15-17 Sept. 2014 doi: 10.1109/CICC.2014.6946021
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:55657
Collection:CaltechAUTHORS
Deposited By: Ruth Sustaita
Deposited On:10 Mar 2015 15:27
Last Modified:03 Oct 2019 08:07

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