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A notation for designing restoring logic circuitry in CMOS

Rem, Martin and Mead, Carver (1982) A notation for designing restoring logic circuitry in CMOS. Microelectronics Journal, 13 (6). pp. 5-10. ISSN 0026-2692. http://resolver.caltech.edu/CaltechAUTHORS:20150313-133632708

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Abstract

A program notation is introduced together with a technique for translating programs in that notation into transistor diagrams for CMOS integrated circuits. A number of restrictions are imposed on the programs ensuring every circuit thus obtained to be restoring. The program notation caters to hierarchical design. It is shown how the observance of the restrictions can be checked for each level of the hierarchy separately. The techniques discussed in this paper may be viewed as a modest step towards silicon compilation.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1016/S0026-2692(82)80130-4DOIArticle
http://www.sciencedirect.com/science/article/pii/S0026269282801304PublisherArticle
Additional Information:© 1982 Benn Electronics Publications. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency, ARPA Order Number 3771, and monitored by the Office of Naval Research under contract number N00014-79-C-0597. This paper is an adaptation of a presentation given at the 2nd Caltech Conference on VLSI, which was held in January 1981.
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Funding AgencyGrant Number
Defense Advanced Research Project Agency (DARPA)3771
Office of Naval Research (ONR)N00014-79-C-0597
Record Number:CaltechAUTHORS:20150313-133632708
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20150313-133632708
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ID Code:55755
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:13 Mar 2015 20:45
Last Modified:13 Mar 2015 20:45

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