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Cost and Performance of VLSI Computing Structures

Mead, Carver A. and Rem, Martin (1978) Cost and Performance of VLSI Computing Structures. In: 3rd USA-Japan Computer Conference proceedings. American Federation of Information Processing Societies , Arlington, VA, pp. 462-467. https://resolver.caltech.edu/CaltechAUTHORS:20150927-230413213

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Abstract

Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. What will the nature of such systems be? How will they be designed? What will be their cost and performance? Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths places a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. A random access memory is analyzed in detail as an example. It is shown that in each case an optimum design is possible, using the area - time product as a cost function.


Item Type:Book Section
Additional Information:Section 26-2-6. This work was supported in part by BMD under contract No. DASG60-77-C-0097 and the Office of Naval Research No. N00014-16-C-0367. California Institute of Technology, Computer Science Dept. Contribution Number 1584.
Funders:
Funding AgencyGrant Number
BMDDASG60-77-C-0097
Office of Naval Research (ONR)N00014-16-C-0367
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Caltech Computer Science Department1584
Record Number:CaltechAUTHORS:20150927-230413213
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150927-230413213
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:60549
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:29 Sep 2015 04:02
Last Modified:03 Oct 2019 08:58

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