A Caltech Library Service

Limitations in Microelectronics - II. Bipolar Technology

Hoeneisen, B. and Mead, C. A. (1972) Limitations in Microelectronics - II. Bipolar Technology. Solid-State Electronics, 15 (8). pp. 891-897. ISSN 0038-1101. doi:10.1016/0038-1101(72)90026-3.

[img] PDF - Updated Version
See Usage Policy.


Use this Persistent URL to link to this item:


The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.

Item Type:Article
Related URLs:
URLURL TypeDescription
Additional Information:© 1972 Pergamon Press. Received 1 December 1971; in revised form 12 January 1972. This work was supported in part by the Office of Naval Research and the General Electric Company.
Funding AgencyGrant Number
Office of Naval Research (ONR)UNSPECIFIED
General ElectricUNSPECIFIED
Issue or Number:8
Record Number:CaltechAUTHORS:20150927-233838341
Persistent URL:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:60553
Deposited On:29 Sep 2015 03:49
Last Modified:10 Nov 2021 22:35

Repository Staff Only: item control page