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A 25Gb/s 170μW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication

Saeedi, Saman and Emami, Azita (2014) A 25Gb/s 170μW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication. In: 2014 IEEE Radio Frequency Integrated Circuits Symposium. IEEE , Piscataway, NJ, pp. 283-286. ISBN 978-1-4799-3862-9.

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A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver's sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage TIA receiver via actual measurements. The proposed receiver architecture achieves error-free operation (BER<;10^(-12)) at 25Gb/s with energy efficiency of 170fJ/b while the conventional receiver achieves error-free operation at 17.1Gb/s with energy efficiency of 260fJ/b.

Item Type:Book Section
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URLURL TypeDescription DOIArticle
Emami, Azita0000-0003-2608-9691
Additional Information:© 2014 IEEE. The authors would like to thank Sylvie Menezo (CEA/LETI) for providing silicon-photonic devices and ST Microelectronics for chip fabrication.
Subject Keywords:high-speed transceivers, hybrid integrated circuits, optical interconnection, sampled-data circuits
Record Number:CaltechAUTHORS:20151013-082613221
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Official Citation:Saeedi, S.; Emami, A., "A 25Gb/s 170μW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication," in Radio Frequency Integrated Circuits Symposium, 2014 IEEE , vol., no., pp.283-286, 1-3 June 2014 doi: 10.1109/RFIC.2014.6851720
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:61025
Deposited By: Tony Diaz
Deposited On:15 Oct 2015 04:23
Last Modified:10 Nov 2021 22:43

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