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An Analog VLSI Chip for Thin-Plate Surface Interpolation

Harris, John G. (1989) An Analog VLSI Chip for Thin-Plate Surface Interpolation. In: Advances in Neural Information Processing Systems 1 (NIPS 1988). Advances in Neural Information Processing Systems. No.1. Morgan Kaufmann , San Mateo, CA, pp. 687-694. ISBN 1-558-60015-9. http://resolver.caltech.edu/CaltechAUTHORS:20160107-160701867

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Abstract

Reconstructing a surface from sparse sensory data is a well-known problem in computer vision. This paper describes an experimental analog VLSI chip for smooth surface interpolation from sparse depth data. An eight-node ID network was designed in 3J.lm CMOS and successfully tested. The network minimizes a second-order or "thinplate" energy of the surface. The circuit directly implements the coupled depth/slope model of surface reconstruction (Harris, 1987). In addition, this chip can provide Gaussian-like smoothing of images.


Item Type:Book Section
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http://papers.nips.cc/paper/169-an-analog-vlsi-chip-for-thin-plate-surface-interpolationOrganizationArticle
Additional Information:© 1989 Morgan Kaufmann. Support for this research was provided by the Office of Naval Research and the System Development Foundation. The author is a Hughes Aircraft Fellow and thanks Christof Koch and Carver Mead for their ongoing support. Additional thanks to Berthold Horn for several helpful suggestions.
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Funding AgencyGrant Number
Office of Naval Research (ONR)UNSPECIFIED
System Development FoundationUNSPECIFIED
Hughes Aircraft CompanyUNSPECIFIED
Record Number:CaltechAUTHORS:20160107-160701867
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20160107-160701867
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:63474
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:15 Jan 2016 00:15
Last Modified:15 Jan 2016 00:15

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