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VLSI Implementation of a High-Capacity Neural Network Associative Memory

Chiueh, Tzi-Dar and Goodman, Rodney M. (1990) VLSI Implementation of a High-Capacity Neural Network Associative Memory. In: Advances in Neural Information Processing Systems 2 (NIPS 1989). Advances in Neural Information Processing Systems. No.2. , San Mateo, CA, pp. 793-800. ISBN 1-55860-100-7. https://resolver.caltech.edu/CaltechAUTHORS:20160107-161736867

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Abstract

In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential correlation associative memory (ECAM). The prototype 3µ-CMOS programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via sub-threshold MOS transistors in this design. The prototype chip is capable of performing one associative recall in 3 µS.


Item Type:Book Section
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http://papers.nips.cc/paper/217-vlsi-implementation-of-a-high-capacity-neural-network-associative-memoryOrganizationArticle
Additional Information:© 1990 Morgan Kaufmann. This work was supported in part by NSF grant No. MIP-8711568.
Funders:
Funding AgencyGrant Number
NSFMIP-8711568
Series Name:Advances in Neural Information Processing Systems
Issue or Number:2
Record Number:CaltechAUTHORS:20160107-161736867
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20160107-161736867
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:63480
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:09 Jan 2016 01:40
Last Modified:03 Oct 2019 09:28

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