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Analog Circuits for Constrained Optimization

Platt, John C. (1990) Analog Circuits for Constrained Optimization. In: Advances in Neural Information Processing Systems 2 (NIPS 1989). Advances in Neural Information Processing Systems. No.2. Morgan Kaufmann , San Mateo, CA, pp. 777-784. ISBN 1-55860-100-7. https://resolver.caltech.edu/CaltechAUTHORS:20160107-162226619

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Abstract

This paper explores whether analog circuitry can adequately perform constrained optimization. Constrained optimization circuits are designed using the differential multiplier method. These circuits fulfill time-varying constraints correctly. Example circuits include a quadratic programming circuit and a constrained flip-flop.


Item Type:Book Section
Related URLs:
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http://papers.nips.cc/paper/245-analog-circuits-for-constrained-optimizationOrganizationArticle
Additional Information:© 1990 Morgan Kaufmann. This paper was made possible by funding from AT&T Bell Labs. Hardware was provided by Carver Mead, and Synaptics, Inc.
Funders:
Funding AgencyGrant Number
AT&T Bell LabsUNSPECIFIED
Series Name:Advances in Neural Information Processing Systems
Issue or Number:2
Record Number:CaltechAUTHORS:20160107-162226619
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20160107-162226619
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:63482
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:09 Jan 2016 02:08
Last Modified:03 Oct 2019 09:28

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