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Analog VLSI Implementation of Multi-dimensional Gradient Descent

Kirk, David B. and Kerns, Douglas (1993) Analog VLSI Implementation of Multi-dimensional Gradient Descent. In: Advances in Neural Information Processing Systems 5 (NIPS 1992). Advances in Neural Information Processing Systems. No.5. Morgan Kaufmann , San Mateo, CA, pp. 789-796. ISBN 1-55860-274-7.

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We describe an analog VLSI implementation of a multi-dimensional gradient estimation and descent technique for minimizing an on-chip scalar function f(). The implementation uses noise injection and multiplicative correlation to estimate derivatives, as in [Anderson, Kerns 92]. One intended application of this technique is setting circuit parameters on-chip automatically, rather than manually [Kirk 91]. Gradient descent optimization may be used to adjust synapse weights for a backpropagation or other on-chip learning implementation. The approach combines the features of continuous multi-dimensional gradient descent and the potential for an annealing style of optimization. We present data measured from our analog VLSI implementation.

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Additional Information:© 1993 Morgan Kaufmann. This work was supported in part by an AT&T Bell Laboratories Ph.D. Fellowship, and by grants from Apple, DEC, Hewlett Packard, and IBM. Additional support was provided by NSF (ASC-S9-20219), as part of the NSF/DARPA STC for Computer Graphics and Scientific Visualization. All opinions, findings, conclusions, or recommendations expressed in this document are those of the author and do not necessarily reflect the views of the sponsoring agencies.
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AT&T Bell LaboratoriesUNSPECIFIED
Series Name:Advances in Neural Information Processing Systems
Issue or Number:5
Record Number:CaltechAUTHORS:20160129-165404707
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:64106
Deposited By: Kristin Buxton
Deposited On:03 Feb 2016 01:00
Last Modified:03 Oct 2019 09:34

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