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Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays

DeHon, André (2005) Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays. In: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05). ACM , New York, NY, pp. 127-137. ISBN 1-59593-029-9. https://resolver.caltech.edu/CaltechAUTHORS:20160419-162745354

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Abstract

Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional lithographic patterning, we show how modestsized PLA logic blocks, which are efficient for implementing logic, can be organized into a segmented, Manhattan mesh interconnection scheme. The resulting programmable architecture has a macro-scale view which is reminiscent of lithographic FPGA and CPLD designs despite the fact that the low-level, sublithographic fabrication techniques used are much more highly constrained than conventional lithography and are prone to high defect rates. Using the Toronto 20 benchmark set, we begin to explore the design space for these sublithographic architectures and show that they may allow us to exploit nanowire building blocks to reach one to two orders of magnitude greater density than 22nm CMOS lithography.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1145/1046192.1046210DOIArticle
http://dl.acm.org/citation.cfm?doid=1046192.1046210PublisherArticle
Additional Information:© 2005 ACM. This research was funded in part by the DARPA Moletronics program under grant ONR N00014-01-0651 and N00014-04-1-0591. Sun Microsystems donated one of the computers used to support this work. This architectural work would not have been possible or meaningful without close cooperation and support from Charles Lieber. The broad mapping study was facilitated by the active support of Deming Chen for PLAMAP. Raphael Rubin, Betta Dawson, and David LeBlanc provided rapid installation of additional computing resources which made it possible to explore the design space as broadly as reported in this work. Michael Hutton provided the BLIFs necessary to remap the Toronto 20 benchmark set for various PLA organizations. The author benefited from valuable discussions with Paul Solomon and Gary Dittlov during the development of this work. This material is based upon work supported by the Department of the Navy, Office of Naval Research. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of the Office of Naval Research.
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Office of Naval Research (ONR)N00014-04-1-0591
Sun MicrosystemsUNSPECIFIED
Office of Naval Research (ONR)N00014-01-0651
Subject Keywords:Design, Sublithographic architecture, nanowires, programmable logic arrays, programmable interconnect, Manhattan mesh
Classification Code:B.6.1 [Logic Design]: Design Styles—logic arrays; B.7.1 [Integrated Circuits]: Types and Design Styles—advanced technologies
DOI:10.1145/1046192.1046210
Record Number:CaltechAUTHORS:20160419-162745354
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20160419-162745354
Official Citation:André DeHon. 2005. Design of programmable interconnect for sublithographic programmable logic arrays. In Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05). ACM, New York, NY, USA, 127-137. DOI=http://dx.doi.org/10.1145/1046192.1046210
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:66287
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:20 Apr 2016 16:33
Last Modified:10 Nov 2021 23:55

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