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Nanowire-Based Programmable Architectures

Dehon, André (2005) Nanowire-Based Programmable Architectures. ACM Journal on Emerging Technologies in Computing Systems (JETC), 1 (2). pp. 109-162. ISSN 1550-4832. doi:10.1145/1084748.1084750.

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Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

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Additional Information:© 2005 ACM. Received June 2005; accepted July 2005. This research was supported by the Defense Advanced Research Projects Agency under ONR contracts N00014-01-0651 and N00014-04-1-0591. This material is based on work supported by the Department of the Navy, Office of Naval Research. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Office of Naval Research.
Funding AgencyGrant Number
Office of Naval Research (ONR)N00014-01-0651
Office of Naval Research (ONR)N00014-04-1-0591
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Subject Keywords:Design, Defect tolerance, Manhattan mesh, nanowires, programmable logic arrays, programmable interconnect, sublithographic architecture, stochastic construction
Issue or Number:2
Classification Code:B.6.1 [Logic Design]: Design Styles—Logic arrays; B.7.1 [Integrated Circuits]: Types and Design Styles—Advanced technologies
Record Number:CaltechAUTHORS:20160420-100045980
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Official Citation:André Dehon. 2005. Nanowire-based programmable architectures. J. Emerg. Technol. Comput. Syst. 1, 2 (July 2005), 109-162. DOI=
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:66306
Deposited On:20 Apr 2016 17:08
Last Modified:10 Nov 2021 23:56

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