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The Impact of Process Scaling on Scratchpad Memory Energy Savings

Redd, Bennion and Kellis, Spencer and Gaskin, Nathaniel and Brown, Richard (2014) The Impact of Process Scaling on Scratchpad Memory Energy Savings. Journal of Low Power Electronics and Applications, 4 (3). pp. 231-251. ISSN 2079-9268. http://resolver.caltech.edu/CaltechAUTHORS:20160421-101256968

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Abstract

Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory. Increases in leakage as a percentage of total power particularly impact applications that rarely access memory. This study examines how the benefits of scratchpad memories have changed in newer processes, based on the measured performance of the WIMS (Wireless Integrated MicroSystems) microcontroller implemented in 180- and 65-nm processes and upon simulations of this microcontroller implemented in a 32-nm process. The results demonstrate that scratchpad memories will continue to improve the power dissipation of many applications, given the leakage anticipated in the foreseeable future.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.3390/jlpea4030231DOIArticle
http://www.mdpi.com/2079-9268/4/3/231PublisherArticle
Additional Information:© 2014 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/). Received: 11 June 2014; in revised form: 22 August 2014; Accepted: 1 September 2014; Published: 9 September 2014. This work was supported by the Engineering Research Center Program of the National Science Foundation under Award No. EEC-9986866. This work made use of University of Utah Shared Facilities supported, in part, by the MRSEC (Materials Research Science and Engineering Centers) Program of the NSF under Award No. DMR-1121252. Chip testing was enabled by the use of VTRAN (a vector translation program) from the kind support of Source III. Chip fabrication was made possible by MOSIS (Metal Oxide Semiconductor Implementation Service, an organization that provides multi-project wafers). Toren Monson assisted in the testing of the 65-nm WIMS microcontroller. Author Contributions: Bennion Redd wrote the first drafts of the text and incorporated the other authors’ feedback, as well as led the testing of the 65-nm WIMS microcontroller on the Verigy 93000. Spencer Kellis and Nathaniel Gaskin led the tape-out process to prepare the chip design for fabrication at MOSIS, and Richard Brown supported and directed work on the WIMS microcontroller, consulted on design decisions, suggested research ideas and offered valuable feedback on revisions of the paper. The authors declare no conflict of interest.
Funders:
Funding AgencyGrant Number
NSFEEC-9986866
NSFDMR-1121252
Subject Keywords:scratchpad memory; loop cache; process scaling; low power; microprocessor; computer architecture; embedded
Record Number:CaltechAUTHORS:20160421-101256968
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20160421-101256968
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:66353
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:21 Apr 2016 17:24
Last Modified:28 Feb 2018 19:54

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