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A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication

Saeedi, Saman and Menezo, Sylvie and Pares, Gabriel and Emami, Azita (2016) A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication. Journal of Lightwave Technology, 34 (12). pp. 2924-2933. ISSN 0733-8724. http://resolver.caltech.edu/CaltechAUTHORS:20160622-132148230

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Abstract

Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 μm pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves −14.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of −10.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JLT.2015.2494060DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7305749PublisherArticle
ORCID:
AuthorORCID
Emami, Azita0000-0003-2608-9691
Additional Information:© 2015 IEEE. Manuscript received July 22, 2015; revised September 25, 2015; accepted October 15, 2015. Date of publication October 25, 2015; date of current version June 1, 2016. The authors would like to thank ST Microelectronics for chip fabrication.
Subject Keywords:energy efficiency, optical receivers, sensitivity, silicon photonics, 3D-integration
Record Number:CaltechAUTHORS:20160622-132148230
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20160622-132148230
Official Citation:S. Saeedi, S. Menezo, G. Pares and A. Emami, "A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication," in Journal of Lightwave Technology, vol. 34, no. 12, pp. 2924-2933, June15, 15 2016. doi: 10.1109/JLT.2015.2494060
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:68595
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:23 Jun 2016 00:20
Last Modified:23 Jun 2016 00:20

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