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An Initial Evaluation of the Tera Multithreaded Architecture and Programming System Using the C3I Parallel Benchmark Suite

Burnett, Sharon and Thornley, John and Ellenbecker, Marrq (1998) An Initial Evaluation of the Tera Multithreaded Architecture and Programming System Using the C3I Parallel Benchmark Suite. In: IEEE/ACM Conference on Supercomputing, 1998. SC98. IEEE Computer Society. , Washington, DC. ISBN 0-8186-8707-X . http://resolver.caltech.edu/CaltechAUTHORS:20160811-164824950

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Abstract

The Tera Multithreaded Architecture (MTA) is a radical new architecture intended to revolutionize high-performance computing in both the scientific and commercial marketplaces. Each processor supports 128 threads in hardware. Extremely fast thread switching is used to mask latency in a uniform-access memory system without caching. It is claimed that these hardware characteristics allow compilers to easily transform sequential programs into efficient multithreaded programs for the Tera MTA. In this paper, we attempt to provide an objective initial evaluation of the performance of the Tera multithreaded architecture and programming system for general-purpose applications. The basis of our investigation is two programs from the C3I Parallel Benchmark Suite (C3IPBS). Both these programs have previously been shown to have the potential for large-scale parallelization. We compare the performance of these programs on (i) a fast uniprocessor, (ii) two conventional shared-memory multiprocessors, and (iii) the first installed Tera MTA (at the San Diego Supercomputer Center). On these platforms, we compare the effectiveness of both automatic and manual parallelization.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/SC.1998.10048DOIPaper
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1437292PublisherPaper
Additional Information:© 1998 IEEE. Thanks to Gail Alverson, John Feo, Kristi Maschhoff, and Allan Porterfield at Tera Computer Company and Wayne Pfeiffer at San Diego Supercomputer Center for their help developing these programs and their comments on this paper. Particular thanks to John Feo for developing the fine-grained solution to the Terrain Masking problem for the Tera MTA. Thanks to Sean Suchter in the Computer Science Department at Caltech for investigating and explaining the Tera MTA to us in the early stages of this work. Thanks to Eric Bogs and Jason Roth in the Computer Science Department at Caltech for developing the Sthreads solutions to the Threat Analysis and Terrain Masking problems on the Pentium Pro platform. Thanks also to our other colleagues in the Computer Science Department and Center for Advanced Computing Research at Caltech for their support of this work. This research was supported by DARPA grant DABT63-97-C-0028, Air Force Office of Scientific Research grant AFOSR-91-0070, and the NSF Center for Research on Parallel Computation (CRPC) under Cooperative Agreement No. CCR-912008.
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)DABT63-97-C-0028
Air Force Office of Scientific Research (AFOSR)AFOSR-91-0070
NSFCCR-912008
Subject Keywords:multithreaded architectures, Tera MTA, C3I Parallel Benchmark Suite, multiprocessor performance evaluation, shared-memory multiprocessors, multithreaded programming, parallel programming, automatic parallelizing compilers, lightweight threads, fine-grained synchronization, Threat Analysis, Terrain Masking, Digital Alpha, HP Exemplar, Intel Pentium Pro
Record Number:CaltechAUTHORS:20160811-164824950
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20160811-164824950
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:69579
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:12 Aug 2016 17:11
Last Modified:12 Aug 2016 17:11

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