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Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator

Bryant, Randal E. and Schuster, Michael D. (1985) Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator. In: 22nd Conference on Design Automation. IEEE , Piscataway, NJ, pp. 715-719. ISBN 0-8186-0635-5.

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This paper presents measurements obtained while performing fault simulations of MOS circuits modeled at the switch level. In this model the transistor structure of the circuit is represented explicitly as a network of charge storage nodes connected by bidirectional transistor switches. Since the logic model of the simulator closely matches the actual structure of MOS circuits, such faults as stuck-open and closed transistors as well as short and open-circuited wires can be simulated. By using concurrent simulation techniques, we obtain a performance level comparable to fault simulators using logic gate models. Our measurements indicate that fault simulation times grow as the product of the circuit size and number of patterns, assuming the number of faults to be simulated is proportional to the circuit size. However, fault simulation times depend strongly on the rate at which the test patterns detect the faults.

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Additional Information:© 1985 IEEE. This research was supported at Caltech by the IBM Corporation and by the Defense Advanced Research Projects Agency, ARPA Order 3771. Michael Schuster was supported in part by a Bell Laboratories Ph.D. Scholarship.
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Defense Advanced Research Projects Agency (DARPA)3771
Bell LaboratoriesUNSPECIFIED
Record Number:CaltechAUTHORS:20160811-165348097
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:69580
Deposited By: Kristin Buxton
Deposited On:12 Aug 2016 17:09
Last Modified:11 Nov 2021 04:16

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