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Nanowire-Based Sublithographic Programmable Logic Arrays

DeHon, André and Wilson, Michael J. (2004) Nanowire-Based Sublithographic Programmable Logic Arrays. In: FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays. ACM , New York, NY, pp. 123-132. ISBN 1-58113-829-6. https://resolver.caltech.edu/CaltechAUTHORS:20161006-125146350

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Abstract

How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottom-up material synthesis techniques to build PLAs using molecular-scale nanowires. Our new designs accommodate technologies where the only post-fabrication programmable element is a non-restoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm^2/or term for a 60 or-term array; a complete 60-term, two-level PLA is roughly the same size as a single 4-LUT logic block in 22nm lithography. Each or term is comparable in area to a 4-transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60- or-term PLA plane will provide equivalent logic to 5–10 4-input LUTs.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1145/968280.968299DOIPaper
http://dl.acm.org/citation.cfm?doid=968280.968299PublisherPaper
Additional Information:© 2004 ACM. This research was funded in part by the DARPA Moletronics program under grant ONR N00014-01-0651. This architectural work would not have been possible or meaningful without close cooperation and support from Charles Lieber. Thanks to Fan Mo for tips on using sis.
Funders:
Funding AgencyGrant Number
Office of Naval Research (ONR)N00014-01-0651
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Subject Keywords:Design, Sublithographic architecture, nanowires, programmable logic arrays
Classification Code:B.6.1 [ Logic Design ]: Design Styles— logic arrays ; B.7.1 [ Integrated Circuits ]: Types and Design Styles— advanced technologies
DOI:10.1145/968280.968299
Record Number:CaltechAUTHORS:20161006-125146350
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20161006-125146350
Official Citation:Andre DeHon and Michael J. Wilson. 2004. Nanowire-based sublithographic programmable logic arrays. In Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays (FPGA '04). ACM, New York, NY, USA, 123-132. DOI=http://dx.doi.org/10.1145/968280.968299
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:70920
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:12 Oct 2016 23:21
Last Modified:11 Nov 2021 04:37

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