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Floating-Point Sparse Matrix-Vector Multiply for FPGAs

deLorimier, Michael and DeHon, André (2005) Floating-Point Sparse Matrix-Vector Multiply for FPGAs. In: FPGA '05 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays. ACM , New York, NY, pp. 75-85. ISBN 1-59593-029-9. https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306

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Abstract

Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Multiply (SMVM) kernel. In fact, it is not uncommon for microprocessors to yield only 10–20% of their peak floating-point performance when computing SMVM. We develop and analyze a scalable SMVM implementation on modern FPGAs and show that it can sustain high throughput, near peak, floating-point performance. For benchmark matrices from the Matrix Market Suite we project 1.5 double precision Gflops/FPGA for a single Virtex II 6000-4 and 12 double precision Gflops for 16 Virtex IIs (750Mflops/FPGA).


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1145/1046192.1046203DOIPaper
http://dl.acm.org/citation.cfm?doid=1046192.1046203PublisherPaper
Additional Information:© 2005 ACM. This work was supported by the Microelectronics Advanced Research Consortium (MARCO) and is part of the efforts of the Gigascale Systems Research Center (GSRC). Thanks to Keith Underwood for valuable editorial comments on this writeup.
Funders:
Funding AgencyGrant Number
Microelectronics Advanced Research Consortium (MARCO)UNSPECIFIED
Gigascale Systems Research Center (GSRC)UNSPECIFIED
Subject Keywords:Algorithm, Performance, Design, Experimentation, Floating Point, FPGA, Reconfigurable Architecture, Sparse Matrix, Compressed Sparse Row
Classification Code:B.7.1 [ Integrated Circuits ]: Types and Design Styles— Algorithms implemented in hardware ; B.2.4 [ Arithmetic and Logic Structures ]: High-Speed Arithmetic— Algo- rithms ; G.1.3 [ Mathematics of Computing ]: Numerical Linear Algebra— Sparse, structu
DOI:10.1145/1046192.1046203
Record Number:CaltechAUTHORS:20161006-130031306
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306
Official Citation:Michael deLorimier and André DeHon. 2005. Floating-point sparse matrix-vector multiply for FPGAs. In Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (FPGA '05). ACM, New York, NY, USA, 75-85. DOI=http://dx.doi.org/10.1145/1046192.1046203
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:70921
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:12 Oct 2016 23:19
Last Modified:11 Nov 2021 04:37

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