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Energy-Delay Efficiency of VLSI Computations

Pénzes, Paul I. and Martin, Alain J. (2002) Energy-Delay Efficiency of VLSI Computations. In: GLSVLSI '02 Proceedings of the 12th ACM Great Lakes symposium on VLSI. ACM , New York, NY, pp. 104-111. ISBN 1-58113-462-2. https://resolver.caltech.edu/CaltechAUTHORS:20161207-165804629

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Abstract

In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the energy and the delay of the computation. We apply this new concept to the parallel and sequential composition of circuits in general and in particular to circuits optimized through transistor sizing. We bound the delay and energy of the optimized circuit and we give necessary and sufficient conditions under which these bounds are reached. We also give necessary and sufficient conditions under which subcomponents of a design can be optimized independently so as to yield global optimum when recomposed. We demonstrate the utility of a minimum-energy function to capture high level compositional properties of circuits. The use of this minimum-energy function yields practical insight into ways of improving the overall energy-delay efficiency of circuits.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1145/505306.505330DOIArticle
http://dl.acm.org/citation.cfm?doid=505306.505330PublisherArticle
Additional Information:© 2002 ACM. We wish to thank the members of the Asynchronous VLSI Group at Caltech for many stimulating discussions: Mika Nyström, Catherine Wong, and Karl Papadantonakis. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)F29601-00-K-0184
Subject Keywords:Theory, Energy-delay optimization, transistor sizing
Classification Code:B.6 [ Hardware ]: Logic Design; B.6.3 [ Logic Design ]: Design Aids| optimization
DOI:10.1145/505306.505330
Record Number:CaltechAUTHORS:20161207-165804629
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20161207-165804629
Official Citation:Paul I Pénzes and Alain J. Martin. 2002. Energy-delay efficiency of VLSI computations. In Proceedings of the 12th ACM Great Lakes symposium on VLSI (GLSVLSI '02). ACM, New York, NY, USA, 104-111. DOI=http://dx.doi.org/10.1145/505306.505330
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:72645
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:08 Dec 2016 03:52
Last Modified:11 Nov 2021 05:04

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