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Transistor sizing of energy-delay-efficient circuits

Pénzes, Paul I. and Nyström, Mika and Martin, Alain J. (2002) Transistor sizing of energy-delay-efficient circuits. In: TAU '02 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems. ACM , New York, NY, pp. 126-133. ISBN 1-58113-526-2. https://resolver.caltech.edu/CaltechAUTHORS:20161207-170651411

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Abstract

This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Etn where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay. We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1145/589411.589439DOIArticle
http://dl.acm.org/citation.cfm?doid=589411.589439PublisherArticle
http://resolver.caltech.edu/CaltechCSTR:2002.003Related ItemTechnical Report
Additional Information:© 2002 ACM. The authors thank Catherine Wong and Karl Papadantonakis for many stimulating discussions. The research reported in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)F29601-00-K-0184
Subject Keywords:Theory, Energy-delay optimization, transistor sizing
Classification Code:B.6 [ Harware ]: Logic Design; B.6.3 [ Logic Design ]: Design Aids— optimization
DOI:10.1145/589411.589439
Record Number:CaltechAUTHORS:20161207-170651411
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20161207-170651411
Official Citation:Paul I. Pénzes, Mika Nyström, and Alain J. Martin. 2002. Transistor sizing of energy-delay--efficient circuits. In Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems (TAU '02). ACM, New York, NY, USA, 126-133. DOI=http://dx.doi.org/10.1145/589411.589439
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:72646
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:08 Dec 2016 03:51
Last Modified:11 Nov 2021 05:04

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