A Caltech Library Service

Design of FPGA interconnect for multilevel metalization

Rubin, Raphael and DeHon, André (2003) Design of FPGA interconnect for multilevel metalization. In: FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays. ACM , New York, NY, pp. 154-163. ISBN 1-58113-651-X.

Full text is not posted in this repository. Consult Related URLs below.

Use this Persistent URL to link to this item:


How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's Mesh-of-Trees, which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge," the Mesh-of-Trees networks require 10% less switches than the standard, Manhattan FPGA routing scheme.

Item Type:Book Section
Related URLs:
URLURL TypeDescription
Additional Information:© 2003 ACM. This research was funded in part by the DARPA Moletronics program under grant ONR N00014-01-0651 and by the NSF CAREER program under grant CCR-0133102.
Funding AgencyGrant Number
Office of Naval Research (ONR)N00014-01-0651
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Subject Keywords:Design, Experimentation, Theory, Mesh-of-Trees, Hierarchical, Multi-level Metalization, FPGA, Interconnect
Classification Code:C.2.1 [ Computer-Communication Networks ]: Network Architecture and Design| Network Topology ; B.7.1 [ Integrated Circuits ]: Types and Design Styles| VLSI
Record Number:CaltechAUTHORS:20161213-164304748
Persistent URL:
Official Citation:Raphael Rubin and André DeHon. 2003. Design of FPGA interconnect for multilevel metalization. In Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays (FPGA '03). ACM, New York, NY, USA, 154-163. DOI=
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:72797
Deposited On:14 Dec 2016 05:25
Last Modified:11 Nov 2021 05:06

Repository Staff Only: item control page