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A multifold coincidence-veto circuit using transistors

Barna, Arpad and Marshall, J. Howard and Sands, Matthew (1961) A multifold coincidence-veto circuit using transistors. Synchrotron Laboratory, CTSL-17. California Institute of Technology , Pasadena, CA. (Unpublished)

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A versatile coincidence-anticoincidence circuit in the 50 nsec time range is described capable of being used with large number of counters. Basic considerations with detailed circuits, operation and performance are given.

Item Type:Report or Paper (Technical Report)
Additional Information:© 1961 California Institute of Technology. This work was supported in part by the U.S. Atomic Energy Commission.
Group:Synchrotron Laboratory
Funding AgencyGrant Number
U. S. Atomic Energy CommissionUNSPECIFIED
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Series Name:Synchrotron Laboratory
Issue or Number:CTSL-17
Record Number:CaltechAUTHORS:20161221-065934762
Persistent URL:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:73042
Deposited By: Ruth Sustaita
Deposited On:21 Dec 2016 16:34
Last Modified:03 Oct 2019 16:24

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