CaltechAUTHORS
  A Caltech Library Service

A multifold coincidence-veto circuit using transistors

Barna, Arpad and Marshall, J. Howard and Sands, Matthew (1961) A multifold coincidence-veto circuit using transistors. Synchrotron Laboratory, CTSL-17. California Institute of Technology , Pasadena, CA. (Unpublished) https://resolver.caltech.edu/CaltechAUTHORS:20161221-065934762

[img] PDF - Submitted Version
See Usage Policy.

8MB

Use this Persistent URL to link to this item: https://resolver.caltech.edu/CaltechAUTHORS:20161221-065934762

Abstract

A versatile coincidence-anticoincidence circuit in the 50 nsec time range is described capable of being used with large number of counters. Basic considerations with detailed circuits, operation and performance are given.


Item Type:Report or Paper (Technical Report)
Additional Information:© 1961 California Institute of Technology. This work was supported in part by the U.S. Atomic Energy Commission.
Group:Synchrotron Laboratory
Funders:
Funding AgencyGrant Number
U. S. Atomic Energy CommissionUNSPECIFIED
Other Numbering System:
Other Numbering System NameOther Numbering System ID
CTSL17
Series Name:Synchrotron Laboratory
Issue or Number:CTSL-17
DOI:10.7907/Z99C6VCB
Record Number:CaltechAUTHORS:20161221-065934762
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20161221-065934762
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:73042
Collection:CaltechAUTHORS
Deposited By: Ruth Sustaita
Deposited On:21 Dec 2016 16:34
Last Modified:03 Oct 2019 16:24

Repository Staff Only: item control page