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Hardware-assisted simulated annealing with application for fast FPGA placement

Wrighton, Michael G. and DeHon, André M. (2003) Hardware-assisted simulated annealing with application for fast FPGA placement. In: FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays. ACM , New York, NY, pp. 33-42. ISBN 1-58113-651-X. https://resolver.caltech.edu/CaltechAUTHORS:20170109-150810119

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Abstract

To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; late-bound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an FPGA implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "FPGA Placement and Routing Challenge" in around 4ms.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1145/611817.611824DOIArticle
http://dl.acm.org/citation.cfm?doid=611817.611824PublisherArticle
Additional Information:© 2003 ACM. This research was funded in part by the DARPA Moletronics program under grant ONR N00014-01-0651 and by the NSF CAREER program under grant CCR-0133102.
Funders:
Funding AgencyGrant Number
Office of Naval Research (ONR)N00014-01-0651
NSFCCR-0133102
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Subject Keywords:Algorithms, Performance, Experimentation, Field-programmable gate arrays, simulated annealing, placement, design automation, reconfigurable computing
Classification Code:B.7.2 [ Integrated Circuits ]: Design Aids - Placement and routing . C.1.3 [ Processor Architectures ]: Multiple datastream architectures – Array and vector processors
DOI:10.1145/611817.611824
Record Number:CaltechAUTHORS:20170109-150810119
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20170109-150810119
Official Citation:Michael G. Wrighton and André M. DeHon. 2003. Hardware-assisted simulated annealing with application for fast FPGA placement. In Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays (FPGA '03). ACM, New York, NY, USA, 33-42. DOI=http://dx.doi.org/10.1145/611817.611824
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:73349
Collection:CaltechAUTHORS
Deposited By:INVALID USER
Deposited On:10 Jan 2017 05:09
Last Modified:11 Nov 2021 05:15

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