Kaviani, Kambiz and Hossain, Masum and Nazari, Meisam Honarvar and Heaton, Fred and Ren, Jihong and Zerbe, Jared (2012) A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS. In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference. IEEE , Piscataway, NJ, pp. 1-4. ISBN 978-1-4673-1556-2. https://resolver.caltech.edu/CaltechAUTHORS:20170201-164230015
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Abstract
A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.
| Item Type: | Book Section | |||||||||
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| Additional Information: | © 2012 IEEE. | |||||||||
| DOI: | 10.1109/CICC.2012.6330684 | |||||||||
| Record Number: | CaltechAUTHORS:20170201-164230015 | |||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20170201-164230015 | |||||||||
| Official Citation: | K. Kaviani, M. Hossain, M. H. Nazari, F. Heaton, J. Ren and J. Zerbe, "A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS," Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, 2012, pp. 1-4. doi: 10.1109/CICC.2012.6330684 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 73969 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | Kristin Buxton | |||||||||
| Deposited On: | 02 Feb 2017 02:40 | |||||||||
| Last Modified: | 11 Nov 2021 05:23 |
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