Pedroni, V. A. and Yariv, A. (1996) Single-clock-cycle two-dimensional median filter. Electronics Letters, 32 (5). pp. 440-441. ISSN 0013-5194. https://resolver.caltech.edu/CaltechAUTHORS:PEDel96
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Abstract
Median filters are of interest to image processing due to their ability to remove impulsive noise. Conventional digital implementations of the median function, however, require multiple clock cycles, a number that is proportional to the size of the 2-D data block. We present in the Letter a complete CMOS implementation, which consumes very little power and computes the median in just one clock cycle, independently from the size of the data block.
Item Type: | Article | ||||||
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Additional Information: | © IEE 1996. | ||||||
Subject Keywords: | median filters, filters, image processing, stack | ||||||
Issue or Number: | 5 | ||||||
Record Number: | CaltechAUTHORS:PEDel96 | ||||||
Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:PEDel96 | ||||||
Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
ID Code: | 747 | ||||||
Collection: | CaltechAUTHORS | ||||||
Deposited By: | Tony Diaz | ||||||
Deposited On: | 26 Sep 2005 | ||||||
Last Modified: | 02 Oct 2019 22:36 |
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