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Fault-tolerant evolvable hardware using field-programmable transistor arrays

Keymeulen, Didier and Zebulum, Ricardo Salem and Jin, Yili and Stoica, Adrian (2000) Fault-tolerant evolvable hardware using field-programmable transistor arrays. IEEE Transactions on Reliability, 49 (3). pp. 305-316. ISSN 0018-9529. http://resolver.caltech.edu/CaltechAUTHORS:20170408-143533356

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Abstract

The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithms) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements and in the environment or faults, through its ability to reconfigure the hardware structure dynamically and autonomously. This capacity for adaptation is achieved via the use of GA search techniques, in our experiments, a fine-grained CMOS (complementary metal-oxide silicon) FPTA (field-programmable FPGA transistor array) architecture is used to synthesize electronic circuits. The FPTA is a reconfigurable architecture, programmable at the transistor level and specifically designed for EHW applications. The paper demonstrates the power of EA to design analog and digital fault-tolerant circuits. It compares two methods to achieve fault-tolerant design, one based on fitness definition and the other based on population. The fitness approach defines, explicitly, the faults that the component can encounter during its life, and evaluates the average behavior of the individuals. The population approach, on the other hand, uses the implicit information of the population statistics accumulated by the GA over many generations. The paper presents experiment results obtained using both approaches for the synthesis of a fault-tolerant digital circuit (XNOR) and a fault-tolerant analog circuit (multiplier).


Item Type:Article
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http://dx.doi.org/10.1109/24.914547DOIArticle
Additional Information:© 2000 IEEE. Manuscript received December 27, 1999. The research in this paper was performed at the Center for Integrated Space Microsystems, Jet Propulsion Laboratory, California Institute of Technology and was sponsored by the “U.S. Defense Advanced Research Projects Agency (DARPA) under the Adaptive Computing Systems Program” and by the U.S. National Aeronautics and Space Administration (NASA). The authors would like to thank A. Thakoor, T. Daud, and R. Tawel of Jet Propulsion Laboratory, for their visionary thinking on evolvable systems, their valuable discussions, and their encouragement and support.
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NASA/JPL/CaltechUNSPECIFIED
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
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Deposited On:25 Apr 2017 22:43
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