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Specifying the Caltech asynchronous microprocessor

Back, R. J. R. and Martin, A. J. and Sere, K. (1996) Specifying the Caltech asynchronous microprocessor. Science of Computer Programming, 26 (1-3). pp. 79-97. ISSN 0167-6423. doi:10.1016/0167-6423(95)00023-2. https://resolver.caltech.edu/CaltechAUTHORS:20170409-083932724

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Abstract

The action systems framework for modelling parallel programs is used to formally specify a microprocessor. First the microprocessor is specified as a sequential program. The sequential specification is then decomposed and refined into a concurrent program using correctness-preserving program transformations. Previously this microprocessor has been specified at Caltech, where an asynchronous circuit for the microprocessor was derived from the specification. We propose a specification strategy that is based on the idea of spatial decomposition of the program variable space.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1016/0167-6423(95)00023-2DOIArticle
Additional Information:© 1996 Elsevier B.V. Back and Sere partially supported by the Academy of Finland.
Funders:
Funding AgencyGrant Number
Academy of FinlandUNSPECIFIED
Issue or Number:1-3
DOI:10.1016/0167-6423(95)00023-2
Record Number:CaltechAUTHORS:20170409-083932724
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20170409-083932724
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:76460
Collection:CaltechAUTHORS
Deposited By: 1Science Import
Deposited On:18 Apr 2017 16:10
Last Modified:03 Oct 2019 17:01

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