Li, Hsin-Yu and Drolet, Jean-Jacques and Psaltis, Demetri and Handschy, Mark A. (1992) Optoelectronic Chip for the Implementation of Back Error Propagation. In: Summer Topical Meeting Digest on Broadband Analog and Digital Optoelectronics, Optical Multiple Access Networks, Integrated Optoelectronics, Smart Pixels. IEEE , Piscataway, NJ, C79-C80. ISBN 0780305221. https://resolver.caltech.edu/CaltechAUTHORS:20170606-170443031
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Abstract
We present a CMOS silicon chip that optically implements the back error propagation (BEP) algorithm [1] of a two layer neural network. The chip has eight units (or "neurons") on a area of approximately 2x2 mm. Each unit consists of a phototransistor as the detector, a modulator pad for light modulation, sample-and-hold circuits, and additional circuits necessary to perform the BEP algorithm.
| Item Type: | Book Section | |||||||||
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| Additional Information: | © 1992 IEEE. | |||||||||
| DOI: | 10.1109/LEOSST.1992.697512 | |||||||||
| Record Number: | CaltechAUTHORS:20170606-170443031 | |||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20170606-170443031 | |||||||||
| Official Citation: | Hsin-Yu Li, J. J. Drolet, D. Psaltis and M. A. Handschy, "Optoelectronic Chip for the Implementation of Back Error Propagation," Summer Topical Meeting Digest on Broadband Analog and Digital Optoelectronics, Optical Multiple Access Networks, Integrated Optoelectronics, Smart Pixels, Santa Barbara, CA, USA, 1992, pp. C79-C80. doi: 10.1109/LEOSST.1992.697512 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 77983 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | INVALID USER | |||||||||
| Deposited On: | 07 Jun 2017 16:24 | |||||||||
| Last Modified: | 15 Nov 2021 17:35 |
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