Dally, William J. and Bryant, Randal E. (1985) A Hardware Architecture for Switch-Level Simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 4 (3). pp. 239-250. ISSN 0278-0070. https://resolver.caltech.edu/CaltechAUTHORS:20170725-174955797
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Abstract
The Mossim Simulation Engine (MSE) is a hardware accelerator for performing switch-level simulation of MOS VLSI circuits [1], [2]. Functional partitioning of the MOSSIM algorithm and specialized circuitry are used by the MSE to achieve a performance improvement of /spl gt/ 300 over a VAX 11/780 executing the MOSSIM II program. Several MSE processors can be connected in parallel to achieve additional speedup. A virtual processor mechanism allows the MSE to simulate large circuits with the size of the circuit limited only by the amount of backing store available to hold the circuit description.
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| Additional Information: | © 1985 IEEE. Manuscript received January 20, 1985; revised March 28, 1985. This research was supported by the Defense Advanced Research Projects Agency, ARPA order number 3771, and monitored by the Office of Naval Research under Contract N00014-79-C-0597. | |||||||||
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| Issue or Number: | 3 | |||||||||
| Record Number: | CaltechAUTHORS:20170725-174955797 | |||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20170725-174955797 | |||||||||
| Official Citation: | W. J. Dally and R. E. Bryant, "A Hardware Architecture for Switch-Level Simulation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 4, no. 3, pp. 239-250, July 1985. doi: 10.1109/TCAD.1985.1270120 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 79368 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | Kristin Buxton | |||||||||
| Deposited On: | 26 Jul 2017 22:48 | |||||||||
| Last Modified: | 03 Oct 2019 18:19 |
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