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Optimum noise performance of transistor input circuits

Middlebrook, R. D. (1958) Optimum noise performance of transistor input circuits. In: 1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol.I. IEEE , Piscataway, NJ, pp. 43-44. https://resolver.caltech.edu/CaltechAUTHORS:20170822-160303586

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Abstract

The single common-emiter transistor amplifier fed from a resistive source exhibits a minimum noise figure, when the source resistance has an optimum value. A generalized amplifier is next shown that is fed from a complex source impedance and containing a single common-emitter transistor in the first stage. It is assumed that noise in succeeding stages is negligible. Various feedback paths to either the base or emitter of the first transistor are shown, and an effective shunt input resistor with thermal noise and an effective emitter degeneration resistor with thernlal noise are given. If the signal source is purely resistive, analysis of the circuit shows that a minimum noise figure is obtainable with an optimum source resistance. If the source is a complex impedance, the quantity of interest is the signal-to-noise ratio (SNR) at the output of the amplifier. This quantity will in general be dependent on the signal frequency chosen, and on the gain characteristics of the entire amplifier. An expression for SNR in the circuit is given. Again, the result is independent of any feedback, except insofar as the feedback affects the gain characteristic. It is to be emphasized that the criteria for best noise performance are in no way connected with the criteria for maximum power transfer from the source.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/ISSCC.1958.1155599DOIArticle
http://ieeexplore.ieee.org/document/1155599/PublisherArticle
Additional Information:© 1958 IEEE.
Record Number:CaltechAUTHORS:20170822-160303586
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20170822-160303586
Official Citation:R. Middlebrook, "Optimum noise performance of transistor input circuits," 1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Philadelphia, PA, USA, 1958, pp. 43-44. doi: 10.1109/ISSCC.1958.1155599
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:80710
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:23 Aug 2017 17:00
Last Modified:03 Oct 2019 18:34

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