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A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLL

Abiri, Behrooz and Hajimiri, Ali (2018) A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLL. In: 2018 IEEE International Solid - State Circuits Conference - (ISSCC). IEEE , Piscataway, NJ, pp. 404-406. ISBN 978-1-5090-4940-0. https://resolver.caltech.edu/CaltechAUTHORS:20180412-125250249

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Abstract

Low-cost mm-wave silicon integrated signal generation and processing enable many applications, such as silicon-based automotive radars for self-driving cars and wireless communications. Some challenges encountered in commercialization of such systems are the high packaging and testing costs and high sensitivity to antenna parameters, which can diminish the advantage of integrated silicon solutions. On-chip antennas have been proposed as a solution to reduce the packaging costs [1,2]. Link budget analysis of systems (e.g., radar) necessitates high-power (high EIRP) transmitters while system resolution analysis suggests higher frequency of operation for better spatial resolution. The scaling of CMOS transistors facilitates the latter requirement, but, unfortunately, the lower breakdown voltage of the transistors reduces their maximum power handling capabilities at a given radiator impedance. Several approaches have already been implemented to address this issue, each with its own shortcoming. Power-combining multiple PA outputs with passive on-chip power combiners [3] adds extra loss and reduces the overall efficiency, spatial power combining using phased arrays [4] consumes a large die area. Power combining at the antenna [5,6] has been proposed as an approach to address these challenges. In this paper, we propose a spatial PA/radiator power combining approach with optimal PA-load design using strongly coupled antennas in close proximity. This approach utilizes techniques of power combining in free space resulting in favorable drive-point impedance design and using on-chip PAs and radiators to achieve high radiated output power.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/ISSCC.2018.8310355DOIArticle
https://ieeexplore.ieee.org/document/8310355PublisherArticle
Additional Information:© 2018 IEEE. The authors would like to thank Dr. Florian Bohn for helpful discussions and Dr. Amirreza Safaripour for assistance in testing. This work was supported by Caltech Innovation Initiative (CI2) research grant.
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Funding AgencyGrant Number
Caltech Innovation Initiative (CI2)UNSPECIFIED
Record Number:CaltechAUTHORS:20180412-125250249
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20180412-125250249
Official Citation:B. Abiri and A. Hajimiri, "A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLL," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 404-406. doi: 10.1109/ISSCC.2018.8310355. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8310355&isnumber=8310156
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:85785
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:12 Apr 2018 20:18
Last Modified:03 Oct 2019 19:35

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