Chen, Kuan-Chang and Emami, Azita (2018) A 25Gb/s APD-based burst-mode optical receiver with 2.24ns reconfiguration time in 28nm CMOS. In: 2018 IEEE Custom Integrated Circuits Conference (CICC). IEEE , Piscataway, NJ, pp. 1-4. ISBN 978-1-5386-2483-8. https://resolver.caltech.edu/CaltechAUTHORS:20180518-134714748
Full text is not posted in this repository. Consult Related URLs below.
Use this Persistent URL to link to this item: https://resolver.caltech.edu/CaltechAUTHORS:20180518-134714748
Abstract
This paper describes an avalanche photodetector (APD) based burst-mode optical receiver in 28nm CMOS with 1-tap feed forward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion to improve the sensitivity. Integrating DC comparator and integrating amplitude comparator are proposed to replace the conventional RC low-pass filters and peak detectors, respectively, to reduce the reconfiguration time for burst-mode operation. The receiver achieves −16dBm sensitivity, 2.24ns reconfiguration time with 5dB dynamic range, and 1.37 pJ/bit energy efficiency at 25Gb/s.
| Item Type: | Book Section | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Related URLs: |
| |||||||||
| ORCID: |
| |||||||||
| Additional Information: | © 2018 IEEE. The authors would like to thank D. A. Nelson, K. Muth, A. Zilkie of Rockley Photonics for their help and support, Caltech MICS Lab members and alumni, A. Agarwal, M. Monge, M. Raj, S. Saeedi, for technical discussions, and Caltech CHIC Lab for sharing testing resources. | |||||||||
| Subject Keywords: | avalanche photodetector (APD); burst-mode; optical; receiver; equalization; reconfiguration; current-integrating | |||||||||
| DOI: | 10.1109/CICC.2018.8357074 | |||||||||
| Record Number: | CaltechAUTHORS:20180518-134714748 | |||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20180518-134714748 | |||||||||
| Official Citation: | K. C. Chen and A. Emami, "A 25Gb/s APD-based burst-mode optical receiver with 2.24ns reconfiguration time in 28nm CMOS," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-4. doi: 10.1109/CICC.2018.8357074 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 86458 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | George Porter | |||||||||
| Deposited On: | 18 May 2018 21:20 | |||||||||
| Last Modified: | 15 Nov 2021 20:38 |
Repository Staff Only: item control page
