CaltechAUTHORS
  A Caltech Library Service

A novel 3D DRAM memory cube architecture for space applications

Agnesina, Anthony and Sidana, Amanvir and Yamaguchi, James and Krutzik, Christian and Carson, John and Yang-Scharlotta, Jean and Lim, Sung Kyu (2018) A novel 3D DRAM memory cube architecture for space applications. In: Proceedings of the 55th Annual Design Automation Conference (DAC '18). Association for Computing Machinery , New York, NY, Art. No. 24. ISBN 978-1-4503-5700-5. http://resolver.caltech.edu/CaltechAUTHORS:20180619-080029891

Full text is not posted in this repository. Consult Related URLs below.

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:20180619-080029891

Abstract

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial-Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency. Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1145/3195970.3195978DOIArticle
Additional Information:© 2018 ACM, Inc.
Record Number:CaltechAUTHORS:20180619-080029891
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20180619-080029891
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:87210
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:19 Jun 2018 16:22
Last Modified:19 Jun 2018 16:22

Repository Staff Only: item control page