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Improved Parylene-Packaged Pentacene Thin-Film Transistors

Lo, Hsi-wen and Tai, Yu-Chong (2008) Improved Parylene-Packaged Pentacene Thin-Film Transistors. ECS Transactions, 11 (25). pp. 51-57. ISSN 1938-6737. doi:10.1149/1.2930793. https://resolver.caltech.edu/CaltechAUTHORS:20180913-133203237

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Abstract

This paper presents improved parylene-packaged thin-film transistors. Several spin-cast dielectrics were investigated to improve the surface roughness of parylene. The corresponding mobility and performance of pentacene thin film transistors were also reported. The relation between pentacene grain sizes and roughness of surfaces where pentacene grows were also investigated. To further improve the mobility, micromachined shadow masks made of silicon and parylene were employed to define the source and drain contacts. The improved pentacene thin-film transistor has a mobility of 0.2 cm^2/V-s and an on/off ratio of 10^4.


Item Type:Article
Related URLs:
URLURL TypeDescription
https://doi.org/10.1149/1.2930793DOIArticle
ORCID:
AuthorORCID
Tai, Yu-Chong0000-0001-8529-106X
Additional Information:© 2008 ECS - The Electrochemical Society. The authors would like to thank Mr. Trevor Roper for his assistance with equipment and fabrication. We would also thank Tanya Owen, Christine Matsuki, Agnes Tong and other members of the Caltech Micromachining Laboratory for their assistance.
Issue or Number:25
DOI:10.1149/1.2930793
Record Number:CaltechAUTHORS:20180913-133203237
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20180913-133203237
Official Citation:Hsi-wen Lo and Yu-Chong Tai Improved Parylene-Packaged Pentacene Thin-Film Transistors ECS Trans. 2008 11(25): 51-57; doi:10.1149/1.2930793
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:89617
Collection:CaltechAUTHORS
Deposited By: George Porter
Deposited On:14 Sep 2018 14:29
Last Modified:16 Nov 2021 00:36

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