Lo, Hsi-wen and Tai, Yu-Chong (2006) Design, Fabrication and Characterization of Parylene-Packaged Thin-Film Transistors. ECS Transactions, 3 (8). pp. 273-278. ISSN 1938-6737. doi:10.1149/1.2356363. https://resolver.caltech.edu/CaltechAUTHORS:20180913-133203426
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Abstract
A micro-fabricated parylene-packaged flexible pentacene thin film transistor is presented. Different from preceding devices that have been reported, this thin film transistor employs parylene as the substrate, the gate insulator and also the encapsulation layer. Also, this thin film transistor uses pentacene, an organic semiconductor with high mobility, as the active material. The transistor consists of Au/Cr gates and Au source and drain electrodes and takes a bottom-contact configuration. The freshly made thin film transistor shows a hole mobility of 0.084809 cm^2/V-s with an on-off ratio of 10^4.
| Item Type: | Article | ||||||
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| Additional Information: | © 2006 ECS - The Electrochemical Society. The authors would like to thank Mr. Trevor Roper for his assistance with equipment and fabrication. We would also thank Tanya Owen, Christine Matsuki and other members of the Caltech Micromachining Laboratory for their assistance. | ||||||
| Issue or Number: | 8 | ||||||
| DOI: | 10.1149/1.2356363 | ||||||
| Record Number: | CaltechAUTHORS:20180913-133203426 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20180913-133203426 | ||||||
| Official Citation: | Hsi-Wen Lo and Yu-Chong Tai Design, Fabrication and Characterization of Parylene-Packaged Thin-Film Transistors ECS Trans. 2006 3(8): 273-278; doi:10.1149/1.2356363 | ||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
| ID Code: | 89619 | ||||||
| Collection: | CaltechAUTHORS | ||||||
| Deposited By: | George Porter | ||||||
| Deposited On: | 13 Sep 2018 23:29 | ||||||
| Last Modified: | 16 Nov 2021 00:36 |
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