Gal-Katziri, Matan and Hajimiri, Ali (2018) A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization. In: 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE , Piscataway, NJ, pp. 231-234. ISBN 978-1-5386-6413-1. https://resolver.caltech.edu/CaltechAUTHORS:20190107-110253682
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Abstract
A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm^2.
| Item Type: | Book Section | ||||||
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| Additional Information: | © 2018 IEEE. This work was sponsored by Caltech’s Space Solar Power Project (SSPP). | ||||||
| Group: | Space Solar Power Project | ||||||
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| Subject Keywords: | CMOS integrated circuits, phased-arrays, radio frequency, tracking loops, delay-lines, phase locked loops, phase noise | ||||||
| DOI: | 10.1109/ASSCC.2018.8579340 | ||||||
| Record Number: | CaltechAUTHORS:20190107-110253682 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20190107-110253682 | ||||||
| Official Citation: | M. Gal-Katziri and A. Hajimiri, "A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization," 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, Taiwan, 2018, pp. 231-234. doi: 10.1109/ASSCC.2018.8579340 | ||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
| ID Code: | 92114 | ||||||
| Collection: | CaltechAUTHORS | ||||||
| Deposited By: | Tony Diaz | ||||||
| Deposited On: | 07 Jan 2019 19:25 | ||||||
| Last Modified: | 16 Nov 2021 03:47 |
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