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A modeling approach and design tool for pipelined central processors

Lang, D. E. and Agerwala, T. K. and Chandy, K. M. (1979) A modeling approach and design tool for pipelined central processors. In: Proceedings of the 6th annual symposium on Computer architecture. Association for Computing Machinery , New York, NY, pp. 122-129.

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As CPUs have become larger and more complex, it has become increasingly more difficult during hardware design and implementation to predict how well a CPU will perform. Furthermore, buyers of such machines have a similar problem in evaluating CPU performance among a diverse selection of computers, since MIP rates quoted by manufacturers may be misleading. This paper describes a methodology based on simulation models for predicting the performance of central processors with instruction execution that occurs in distinct and separable phases. The basic components of the model have been designed to allow a functional representation of the instruction execution path. This provides a natural mapping of the instruction set onto the architecture in a manner familiar to the designer. The model has been verified for existing computers using actual trace data from these machines. Novel aspects of the model and its use in CPU design are discussed.

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Additional Information:© 1979 IEEE. This work was supported in part by an AAUW/IBH Fellowship and a University of Texas Office of Graduate Studies Travel Grant.
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American Association of University WomenUNSPECIFIED
University of TexasUNSPECIFIED
Record Number:CaltechAUTHORS:20190114-100604653
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:92249
Deposited By: Tony Diaz
Deposited On:14 Jan 2019 20:50
Last Modified:16 Nov 2021 03:48

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