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Interface Roughness Effects in Ultra-Thin Tunneling Oxides

Ting, D. Z.-Y. and Daniel, Erik S. and McGill, T. C. (1998) Interface Roughness Effects in Ultra-Thin Tunneling Oxides. VLSI Design, 8 (1-4). pp. 47-51. ISSN 1065-514X.

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Advanced MOSFET for ULSI and novel silicon-based devices require the use of ultrathin tunneling oxides where non-uniformity is often present. We report on our theoretical study of how tunneling properties of ultra-thin oxides are affected by roughness at the silicon/oxide interface. The effect of rough interfacial topography is accounted for by using the Planar Supercell Stack Method (PSSM) which can accurately and efficiently compute scattering properties of 3D supercell structures. Our results indicate that while interface roughness effects can be substantial in the direct tunneling regime, they are less important in the Fowler-Nordheim regime.

Item Type:Article
Additional Information:Released under a “Creative Commons Attribution License,” enabling the unrestricted use, distribution, and reproduction of an article in any medium, provided that the original work is properly cited. The authors would like to thank O.J. Marsh for helpful discussions. This work was supported by the U.S. Office of Naval Research (ONR) under Grant No. N00014-92-J-1845, and by the ROC National Science Council under Grant No. NSC 86-2112-M-007-001. Special Issue: Fifth International Workshop on Computational Electronics, University of Notre Dame, 28-30 May 1997, VLSI Design 8(1-4) 1998.
Subject Keywords:Ultrathin, oxide, SiO2, tunneling, interface roughness
Record Number:CaltechAUTHORS:TINvd98b
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Official Citation:D. Z.-Y. Ting, Erik S. Daniel, and T. C. Mcgill, “Interface Roughness Effects in Ultra-Thin Tunneling Oxides,” VLSI Design, vol. 8, no. 1-4, pp. 47-51, 1998. doi:10.1155/1998/23567
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:9256
Deposited By: Archive Administrator
Deposited On:01 Dec 2007
Last Modified:26 Dec 2012 09:47

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