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A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS

Nazari, Meisam Honarvar and Emami-Neyestanak, Azita (2013) A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS. In: 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE , Piscataway, NJ, pp. 257-260. ISBN 978-1-4673-6062-3/13. https://resolver.caltech.edu/CaltechAUTHORS:20190213-083456432

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Abstract

A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER<; 10^(-12). It has better than 136fJ/b of power efficiency at 10Gb/s. The total area of the transmitter and receiver is 1110μm^2.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/RFIC.2013.6569576DOIArticle
ORCID:
AuthorORCID
Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:© 2013 IEEE.
Subject Keywords:Interconnect, On-chip signaling, Double-sampling, Dynamic offset modulation, Crosstalk
DOI:10.1109/RFIC.2013.6569576
Record Number:CaltechAUTHORS:20190213-083456432
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20190213-083456432
Official Citation:M. H. Nazari and A. Emami-Neyestanak, "A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS," 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, 2013, pp. 257-260. doi: 10.1109/RFIC.2013.6569576
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:92871
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:13 Feb 2019 18:32
Last Modified:16 Nov 2021 16:54

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